DK-DEV-5SGXEA7N【PDF 159/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51007

2014.01.10

Figure 6-3: LVDS SERDES

SERDES I/O Standards Support in Stratix V Devices

6-3

Serializer

2

IOE

IOE supports SDR, DDR, or non-registered datapath

tx_in

10

DIN DOUT

+

–

tx_out

10 bits

maxiumum

data width

tx_coreclock

3

(LVDS_LOAD_EN, diffioclk, tx_coreclock)

LVDS Transmitter

IOE

rx_out

10

IOE supports SDR, DDR, or non-registered datapath

2

Deserializer

Bit Slip

Synchronizer

LVDS Receiver

DPA Circuitry

+

–

rx_in

10

FPGA

DOUT

DIN

DOUT

DIN

DOUT

DIN

Retimed

Data

DIN

Fabric

2

diffioclk

DPA Clock

(LOAD_EN,

rx_divfwdclk

rx_outclock

diffioclk)

Clock Mux

3

(DPA_LOAD_EN,

DPA_diffioclk, rx_divfwdclk)

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

8 Serial LVDS

Clock Phases

DPA Clock Domain

LVDS Clock Domain

Fractional PLL

rx_inclock / tx_inclock

The preceding figure shows a shared PLL between the transmitter and receiver. If the transmitter and receiver

do not share the same PLL, you require two fractional PLLs. In single data rate (SDR) and double data rate

(DDR) modes, the data width is 1 and 2 bits, respectively.

The ALTLVDS transmitter and receiver requires various clock and load enable signals from a fractional

PLL. The Quartus II software configures the PLL settings automatically. The software is also responsible for

generating the various clock and load enable signals based on the input reference clock and selected data

rate.

Note: For the maximum data rate supported by the Stratix V devices, refer to the device overview.

Related Information

? Stratix V Device Overview

? LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide

Provides a list of the LVDS transmitter and receiver ports and settings using ALTLVDS.

? Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-8

SERDES I/O Standards Support in Stratix V Devices

The following tables list the I/O standards supported by the SERDES receiver and transmitter, and the

respective Quartus II software assignment values.

The SERDES receiver and transmitter also support all differential HSTL, differential HSUL, and differential

SSTL I/O standards.

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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